With recent advances in the development of high density very large scale integration (VLSI) circuits, the dimensions of the devices continue to shrink resulting in a corresponding decrease in the gate oxide thicknesses in the CMOS devices. This decrease, relative to breakdown voltage, has resulted in the greater susceptibility of these devices to damage from the application of excessive voltages such as caused by an electrostatic discharge (ESD) event. During an ESD event, charge is transferred between one or more pins of the integrated circuits and another conducting object in a short period of time, typically less than one microsecond. The charge transfer generates voltages that are large enough to break down insulating films, e.g., gate oxides on MOSFET devices, or that can dissipate sufficient energy to cause electrothermal failures in the devices. Such failures include contact spiking, silicon melting, or metal interconnect melting. Consequently, in order to deal with transient ESD pulses, an integrated circuit must incorporate protection circuits at every input and I/O pin. Various circuit structures for ESD protection can be found, e.g., in U.S. Pat. Nos. 5,019,888 to Scott et al; 5,182,220 to Ker et al, 5,218,222 to Roberts; and 5,329,143 to Chan; and in the literature in "Internal Chip ESD Phenomena Beyond the Protection Circuit", C. Duvvury, IEEE Transactions on Electron Devices, Vol .35, No. 12, December 1988; "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", A. Chatterjee, IEEE Electron Device Letters, Vol. 12, No. 1, January 1991; and "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50- and 0.25-.mu.m Channel Length CMOS Technologies", S. Voldman, EOS/ESD Symposium Proceedings, pp. 125-134, 1994.
An example of one form of ESD protection device of the type discussed in the above-cited "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", A. Chatterjee, IEEE Electron Device Letters, Vol. 12, No. 1, January 1991 paper is shown in FIG. 1, which is a cross-sectional view of a known low-voltage threshold silicon controlled rectifier (LTVSCR) integrated circuit (IC) device 10 fabricated from a semiconductor substrate 12 of a first conductivity type, such as P-type conductivity, with various diffusions and circuit components formed thereon to provide protection against ESD damage due to excessive stresses. The SCR is known in the art as an ideal device for on-chip protection against ESD since in its ON state it protects sensitive devices by virtue of its comparatively low resistance. Also, the failure threshold of the SCR is high because the heat generation is distributed over a large volume. However, there are sensitive devices that are damaged at voltages less than the SCR trigger voltage, which typically is comparatively high, so that the SCR alone is insufficient for protecting devices such as NMOS transistors which have the lowest breakdown voltage in CMOS technology. For example, the trigger voltage of a lateral SCR is approximately 50 V, as compared to an NMOS transistor drain breakdown voltage of less than 15 V. To achieve a reduction of the SCR trigger voltage to a level less than the NMOS breakdown voltage, an NMOS-like structure is incorporated in the SCR device as a trigger. Accordingly, a thin-oxide NMOS field-effect transistor (MOSFET) 26, is shown in the FIG. 1 device in the form of an N-channel device, composed of N+ regions, 18 and 20, having a gate electrode 22 with a thin oxide 24 therebetween. The inner N+ region 20 of MOSFET 26 is connected to internal circuits 30 and its outer N+ region 18 is coupled to an adjacent outer P+ conductivity region 14 by a contact or bus 16 which is connected to a negative voltage source VSS or ground. The Vss source is also coupled to the gate electrode 22 to keep the LVTSCR OFF during normal operation. In the absence of the SCR, the NMOS thick-field device 26 would deal with either positive or negative ESD stresses developed between the Vss voltage on contact 16 and the voltage communicated from the internal circuits 30. The N+ diffusion regions, 18 and 20, and underlying P-type substrate 12 act as a bipolar device when there is an excessive positive stress on the internal circuit 30 with respect to Vss, i.e., a parasitic lateral NPN transistor results, with its base at the substrate 12, its emitter at N+ region 18, and its collector or drain at N+ region 20. The NP junction (20,12) at the drain breaks down, typically at about 13 volts, to offer protection to the other circuit devices, and the generated electrons are swept into the collector region 20. The generated holes injected into the base region 12 cause the substrate voltage to increase, forward biasing the emitter junction, and causing the NPN transistor to turn ON. As a consequence, injection of electrons from the emitter 18 into the base 12 is increased and those electrons reaching the collector-base junction (20,12) generate new electron hole pairs and current growth continues. This "positive feedback" would cause the emitter-to-collector current to increase indefinitely, resulting in damage to the device if the current is not somehow limited. Also, in the absence of the SCR, when a negative stress on the internal circuit with respect to Vss occurs, a forward biased diode would result between P+ region 14 and N+ region 20, through the substrate 12, that would turn ON to protect the other internal integrated devices.
To complete the LVTSCR, an N-well 28 is provided in substrate 12 that substantially overlaps N+ region 20 and extends laterally beyond a second N+ region 32 which is coupled to an adjacent inner P+ conductivity region 34 by a contact or bus 36 connected to an I/O Pad. N-well 28 increases the junction breakdown voltage between N+ region 20 and the substrate 12, and alleviates the chances of contact spiking produced by the N+ junction and thus avoids short circuiting of the N+ junction to the P-substrate. Moreover, even were a breakdown to occur in the N+ junction, the increased cross-sectional area of the N-well 28 available for current flow decreases the current density and thus improves the ESD immunity. In this arrangement the NMOS-like device acts as a trigger for the SCR. The internal circuits connection acts as a "drain tap"and the N+ region 18 source as a cathode, and the charge generated during avalanche breakdown near the drain tap triggers the LVTSCR. Prior to triggering, the LVTSCR characteristics resemble that of an NMOS with the same gate length, and since for short channel MOSFETs the drain breakdown voltage decreases with reduction of the gate length, if the gate length of the LVTSCR is kept less than that of an NMOS of the output buffer in parallel with it and at the same potential, then the LVTSCR will fire first and protect the NMOS.
There exists a danger, since the N-well is lightly doped, that the SCR turn-on voltage may still be so high that the gate oxide of NMOS devices may become damaged. Thus, the LVTSCR device turn-on voltage is dependent on the NMOS beakdown voltage. It is therefore desirable to be able to reduce the trigger voltage required to turn ON a protective SCR as much as possible.
It is therefore an object of the present invention to provide an enhanced ESD protection performance apparatus and method for protecting VLSI circuits and particularly CMOS devices by reducing the trigger voltage required to turn ON a protective SCR.
It is another object of the present invention to provide an enhanced ESD protection performance apparatus and method utilizing an improved SCR structure with a low turn-on voltage.
It is a further object of the present invention to provide an improved SCR for enhanced ESD protection performance using a P-LDD dosage in the SCR trigger structure to create an N+-P-LDD junction with a reduced breakdown voltage.